IS200TRLYH1BED /FD /GF GE Mark VI

IS200TRLYH1BED /FD /GF GE Mark VI

Item Number:IS200TRLYH1BED

Price: $2000



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Technické parametry
IS200TRLYH1B is a relay terminal board for GE Mark VI steam turbine control system. It can perform various tests such as electrical overspeed trip test, mechanical trip piston test, mechanical overspeed trip test, etc. to ensure system safety. As a terminal relay card, it receives controller signals, controls the operation of steam turbine related equipment, and achieves precise control.

IS200TRLYH1B GE

 

 

 

IS200TRLYH1BED
IS200TRLYH1B

30*20*10cm

0.65kg

 

IS200TRLYH1B appearance structure:
Terminal blocks: There are two large black terminal blocks on the left edge, each with 24 silver metal terminals, a total of 48, all with white markings.
Connector ports: There are 4 connector ports on the right edge, 3 of which are arranged vertically and 1 is located parallel at the bottom.
 
Number of relay channels on one TRLY_1B board
12:
6 relays with optional solenoid driver voltages
5 relays with dry contacts only
1 relay with 7 A rating
Nominal 125 V dc or 24 V dc
Nominal 115/230 V ac
0.6 A for 125 V dc operation
3.0 A for 24 V dc operation
3.0 A for 115/230 V ac, 50/60 Hz operation
6 A at 115 V ac for relay 12 only

 

24 V dc voltage current rating 10 A, resistive current rating 2 A, L/R=7 ms, without suppression
125 V dc voltage current rating 0.5 A, resistive current rating 0.2 A, L/R=7 ms, without
125 V dc voltage current rating 0.5 A, resistive current rating 0.65 A, L/R=150 ms,
Electrical operations: 100,000
Mechanical operations: 10,000,000
Unplugged cable or loss of communication with I/O board: relays de-energize if
 
• The solenoid excitation voltage is monitored downstream of the fuses and an alarm is latched if it falls below 12 V dc.
• If any one of the outputs goes unhealthy a composite diagnostics alarm,L3DIAG_xxxx occurs.
• Each terminal board connector has its own ID device that is interrogated by the I/O pack/board. The connector ID is coded into a read-only chip containing the board serial number, board type, revision number, and the JA1/JR1/JS1/JT1 connector location. When the chip is read by the I/O processor and mismatch is encountered, a hardware incompatibility fault is created.
 
 
 
 
 
 
 

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